By Professor Memory | February 16, 2010
In response to a question to name a specific application for a particular memory technology, I responded that the value proposition of any technology is related to the specific end application and that therefore the market scenario had to be first identified.
One possible scenario is that nothing changes from today in which existing applications were designed with the specific cost/performance attributes of NAND and DRAM in mind. I agree with the argument that it will be difficult for new memory technologies to compete with NAND and DRAM in existing applications assumes that technology challenges of reducing storage mass for memory cells alone not be enough to sustain high volume growth for new and emerging technologies. Hard-working and clever engineers seem to have gotten us past one insurmountable barrier after another.
Another possible scenario begins with the market competition of SoC and SiP as single-core processors take on a new role and with the increasing challenges of maintaining traditional declines in the cost per bit of established memory technologies. To me, these are indications of fundamental shifts in what can be accomplished by semiconductor technologies—as well as shifts in what semiconductor technologies are expected to accomplish.
There are two fundamental tenets of which I am a strong believer. The first is Moore’s Law. While I still hold it to be more of an accepted guideline for memory suppliers simply because charge storage in a constantly shrinking mass is contrary to the performance advantages of energy moving through logic circuitry at the speed of light, nevertheless Moore’s Law has guided general semiconductor trends because it has achieved the anticipated increases in performance in logic circuitry.
The other tenet I believe to be significant is Makimoto’s Wave (first published in 1991), which predicts the ebb and flow between specialization and generalization of product development.
Source: Electronics Weekly, Jan. 1991/Dr. T. Makimoto TechnoVision
From one interpretation of Dr. Tsugio Makimoto’s theory: “When large numbers of new technologies such as devices, architectures and software appear, the semiconductor industry as a whole moves toward standardization. Aspects such as the need for product differentiation and added value then appear, and the imbalance between supply and demand suppresses the large swinging of the pendulum. In the other direction, progress in design automation and advances in technologies occur, shifting the semiconductor industry to customization.”
Today’s technology challenges for FPGA’s and charge storage memories, the growing commoditization of general-purpose single-core processors in keeping with Christensen’s “Innovator’s Dilemma,” increasing focus on So. by the semiconductor industry’s largest company, and the rise of flexible packaging technologies supporting multiple die are all aligned with a general shift toward customized solutions that is consistent with Dr. Makimoto’s observations of semiconductor trends made almost 20 years ago.
This long and winding road leads me to believe that we are approaching a new wave of customized solutions concurrent with the increased complexity of traditional charge storage memory technologies. I surmise that the convergence of these two trends will lead to a richer and broader set of target applications for memory technologies than we have seen in the previous PC-driven cycle of memory technology development. We are shifting toward a wider range of target applications for memory technologies, which in turn will likely improve the value proposition of the growing set of new memory technologies, and therein lies the future market opportunities for new and emerging memory technologies, new packaging concepts, and new logic architectures.
Introduction to the UNIO EEPROM Family Part 1 of 2
When small size or I/O resources on the microcontroller are a concern and non-volatile memory is required, the UNI/O EEPROM Family is another option. This seminar begins with a brief overview of the serial buses used in today's mainstream EEPROMs, followed by a comparison of the new UNI/O Bus protocol. Since this new bus only uses a single I/O port for communication, it gives engineers another option for miniaturization and lower system costs. As the seminar progresses, the main features of this new memory are shown along with the advanced features never before seen in a single EEPROM device. Finally, there is a discussion on an easy way to evaluate UNI/O EEPROMs using existing customer hardware and Microchip's software drivers.